The Xilinx FPGA-based PICMG ATCA™ 3.0 Design Kit is the first solution stemming from the joint effort between Avnet and Xilinx to accelerate adoption of the ATCA PICMG standard for high-speed networking and communication designs. Access to affordable, standardized and scalable platforms is paramount to addressing the challenges of next-generation systems.
The PICMG 3.0, 2.5G Full-Mesh Reference Design can be used as a development platform for PICMG 3.0 full-mesh line cards supporting system configurations of up to 16-cards and port rates to 2.5 Gbps. The heart of the reference design is the Virtex-II Pro device with RocketIO MGTs, serving as the interface to the full-mesh backplane. The full-mesh card also allows application flexibility by reserving an area of the board for a pluggable "personality module" (PM).
Standards Supported:
Solutions Supported:
- Broadband Infrastructure > CMTS
- Broadband Infrastructure > DSLAM
- Broadband Infrastructure > Mini-DSLAM
- Broadband Infrastructure > Other
- Metro/Edge > Core Router
- Metro/Edge > Metro/Edge Router
- Metro/Edge > Multi-Service Provisioning Platform
- Metro/Edge > Multi-Service Switch
- Metro/Edge > Other
- Networked Storage > NAS
- Networked Storage > SAN Disk Array
- Networked Storage > SAN Management Appliance
- Networked Storage > SAN Modular Switch
Operating Systems Supported:
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Comments
Yang Choong Reol on October 08, 2008
According to IEEE802.3ba, Backplane with 4 x10GBASE-KR will support 40GBASE-KR4(4 lane, serial).
I am looking for the ATCA platform equipped backplane for 40GBASE-KR4(4 lane, serial).